1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and, more particularly, to transistors comprising a silicon/germanium alloy layer deposited onto the surface of the active region of the transistor.
2. Description of the Related Art
The ongoing trend in electronics towards more and more complex integrated circuits requires the dimensions of electronic devices to decrease, in order to achieve a higher and higher integration density.
Transistors are the dominant circuit elements in current integrated circuits. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density.
Among the various fabrication technologies of integrated circuits, the CMOS technology is currently the most promising approach, since it enables producing devices with superior characteristics in terms of operating speed, power consumption and cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed in active regions defined within a semiconductor layer supported by a substrate.
Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials such as, for example, dopant atoms or ions may be introduced into the original semiconductor layer.
A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises a source and a drain region, highly doped with dopants of the same species. An inversely or weakly doped channel region is then arranged between the drain and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, may be controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on, among other things, the mobility of the charge carriers and on the distance along the transistor width direction between the source and drain regions, which is also referred to as channel length. For example, by reducing the channel length, the channel resistivity decreases. Thus, an increased switching speed and higher drive current capabilities of a transistor may be achieved by decreasing the transistor channel length.
However, reduction of transistor channel length may not be pushed to extreme limits without incurring other problems. For example, the capacitance between the gate electrode and the channel decreases with decreasing channel length. This effect must then be compensated for by reducing the thickness of the insulating layer between the gate and the channel. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high speed transistor elements. Such small thicknesses of the insulating layer might, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, other alternatives have been developed in order to increase the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors.
One promising approach in this respect is the generation of a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors.
In silicon-based transistors, a semiconductor alloy with the same crystal structure as silicon but with a slightly greater lattice constant may be used for applying a desired amount of compressive stress in the channel region of a PFET transistor. For example, a silicon/germanium (SiGe) alloy with a variable concentration of germanium (Ge) may be used.
SiGe or other semiconductor alloys may be used for fabricating improved P-channel FETs in two different ways.
One method consists of embedding the semiconductor alloy in the active region at the ends of the channel region. For example, after forming the gate electrode structure, corresponding cavities may be formed laterally adjacent to the gate electrode structure in the active region. The cavities thus formed may then be filled with the silicon/germanium alloy which, when grown on the silicon material, generally experiences an internal compressive strain. This strain may then induce a corresponding compressive strain component in the adjacent channel region. Consequently, a plurality of process strategies has been developed in the past in order to incorporate a highly strained silicon/germanium material in the drain and source areas of P-channel transistors. A silicon/germanium or, in general, a semiconductor alloy material used in the manner described above will hereinafter be referred to as “embedded SiGe” or “embedded semiconductor alloy,” respectively.
Alternatively or additionally, a thin SiGe layer may be deposited directly onto a single crystal silicon layer so as to form an SiGe channel for the PFET. Semiconductor alloy layer is mainly provided for modulating the work function of the P-channel FET. Due to the lattice mismatch between crystalline Si and SiGe, the thin SiGe layer grown on the Si surface is highly strained, which increases hole mobility in the semiconductor alloy layer. According to some fabrication techniques, a thin SiGe layer in the channel region is necessary in order to modulate the work function of the P-channel FET. This is the case, for example, with the implementation according to the gate-first high-k/metal gate procedure, especially with gate electrodes of a length of 32 nm or smaller. An SiGe or, in general, a semiconductor alloy layer formed as described above will hereinafter be referred to as “channel SiGe layer” or “channel semiconductor alloy layer,” respectively.
The known problem when using a semiconductor alloy, such as SiGe, during PFET fabrication is related to the formation of a “spotty,” i.e., non-continuous, layer of metal silicide in correspondence to the portions of the semiconductor structure surface exposing SiGe.
A metal silicide layer, preferably nickel silicide (NiSi), is formed on the surface portions of the semiconductor structure which are to be electrically contacted in order to reduce the sheet resistance of silicon contact regions. However, when formed in correspondence to surface areas exposing SiGe, the silicide layer has been observed to agglomerate and cluster due to the thermal budget undergone by the semiconductor structure during subsequent stages of the device fabrication process flow. In particular, as will be clarified in the following, the SiNi layer forming an interface with SiGe tends to agglomerate into isolated clusters during heating steps performed at a temperature in the range of 400-500° C. after formation of the SiNi layer and/or after formation of a stressed material layer on top of the exposed face of the semiconductor structure.
FIG. 1a shows the formation of a spotty SiNi layer in a typical PFET including a channel SiGe layer as produced by following the teachings of the prior art.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor structure 100 in an advanced manufacturing stage. As shown, the device 100 comprises a substrate 101, such as a semiconductor material and the like, above which a semiconductor layer 102 is formed. The semiconductor layer 102 is typically made of a silicon single crystal. The semiconductor layer 102 is laterally divided into a plurality of active regions 102a, which are to be understood as semiconductor regions in and above which one or more transistors are to be formed. For convenience, a single active region 102a is illustrated, which is laterally delimited by an isolation region 102b, such as a shallow trench isolation. Depending on the overall device requirements, the substrate 101 and the semiconductor layer 102, for instance initially provided as a silicon material, may form an SOI (silicon-on-insulator) architecture when a buried insulating material (not shown) is formed directly below the semiconductor layer 102. In other cases, initially the semiconductor layer 102 represents a part of the crystalline material of the substrate 101 when a bulk configuration is to be used for the device 100.
The semiconductor structure 100 includes a P-channel FET 150 formed in and above the active region 102a. The transistor 150 includes highly doped drain and source regions 151 formed in the active region 102a. Drain and source regions 151 also include extension regions 151e, which are regions determining the length of the channel region 155.
A semiconductor alloy layer 104, typically an SiGe layer, lies on top of the upper surface 102u of the semiconductor layer 102. In particular, the SiGe layer 104 is formed on the upper surface 102u of the silicon layer 102 within active region 102a. The upper surface 102u of the semiconductor layer 102 may be indented in correspondence to active regions 102a in order to accommodate the SiGe layer 104, as shown in FIG. 1a. The semiconductor alloy layer 104 is formed on the silicon upper surface 102u so that a portion thereof is included in the transistor channel region 155, thus forming a part thereof. Thus, the semiconductor alloy 104 is a channel semiconductor alloy layer.
The transistor 150 further includes a gate electrode structure 160 formed on the channel semiconductor alloy layer 104 and, in particular, on its upper or exposed surface 104u. The gate electrode 160 may have any appropriate geometric configuration, for instance in terms of length and width. For example, the gate length, i.e., in FIG. 1a, the horizontal extension of an electrode material 162 of the gate electrode structure 160, may be 50 nm and less. An insulation layer 161 physically and electrically separates the gate electrode material 162 from the channel region 155 of the transistor 150.
Depending on the configuration of the gate electrode structure 160, the insulation layer 161 and gate electrode material 162 may be formed in different ways. For example, if the gate electrode 160 is a conventional oxide/polysilicon gate electrode (polySiON), then the gate insulation layer 161 may be formed from a conventional gate dielectric material, such as, for example, silicon dioxide, silicon oxynitride and the like, whereas the gate electrode material 162 may comprise polysilicon. Alternatively, a high-k dielectric/metal gate electrode (HKMG) configuration may be preferred for the gate electrode structure 160. In this case, the insulation layer 161 may be one of the high-k gate dielectric materials well known in the art. By high-k material it is referred to a material with a dielectric constant “k” higher than 10. Examples of high-k materials used as insulating layers in gate electrodes are tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2) and the like.
The gate electrode structure 160 may also have a gate metal layer 162a, for instance in the form of tantalum nitride and the like, possibly in combination with a work function metal species, such as aluminum and the like. The gate metal layer 162a is typically formed above the insulation layer 161, thereby adjusting an appropriate work function and thus threshold voltage of the transistor 150. Furthermore, the gate electrode structure 160 may be laterally delimited by a spacer structure 163 which may include one or more dielectric materials such as, for example, silicon nitride, silicon dioxide, silicon oxynitride and the like. For example, the structure 163 may include appropriate protective liner materials for laterally encapsulating sensitive gate materials, such as the insulation layer 161 and, in particular, the metal layer 162a. 
FIG. 1b shows semiconductor structure 100 in a subsequent stage of the fabrication process flow, wherein a refractory metal layer 108 is deposited onto the exposed face of the semiconductor structure. In particular, the refractory metal layer 108 is deposited onto the upper surface 104u of the semiconductor alloy layer 104 using a suitable material deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) and the like. The layer 108 includes one or more refractory metals which are adapted to form a metal silicide layer in correspondence to portions of the semiconductor structure exposing the gate electrode material 162 and source or drain regions 151. Thus, the refractory metal layer 108 may comprise, for example, one metal such as nickel, titanium, cobalt and the like. Preferably, the refractory metal layer 108 comprises nickel. The refractory metal layer 108 may also comprise platinum, which in some cases may promote a more homogeneous formation of nickel monosilicide.
After deposition of the refractory metal layer 108, a heat treatment process 180 may be performed so as to initiate a chemical reaction between the nickel atoms in the layer 108 and the silicon atoms in those areas of the source and drain regions 151 and the gate electrode material 162 that are in contact with the nickel, thereby forming nickel silicide regions that substantially comprise low-resistivity nickel monosilicide. The heat treatment process 180 is generally a two-step process. A first heat treatment step is performed in the range of approximately 300-400° C. for a time period of approximately 30-90 seconds. After the first heat treatment step, any non-reacted nickel material from the refractory metal layer 108 is selectively removed by one of a variety of well-known etch/cleaning processes. Finally, a second heat treatment step is performed in the range of approximately 400-500° C., again for a time period of approximately 30-90 seconds. It should be noted that the silicon material contained in the sidewall spacer structures 163 and the isolation regions 102b does not substantially take part in the chemical reaction induced during the heat treatment process 180, as it is present in those features only as a thermally stable silicon dioxide and/or silicon nitride material.
In FIG. 1 c, the semiconductor structure 100 is shown after the deposition of the refractory metal layer 108 and application of heat treatment 180. As a result of the heat treatment 180, a metal silicide layer 162b has formed partly in and partly on top of the upper surface of the gate electrode material 162, which was exposed before depositing the refractory metal layer 108. Analogously, a metal silicide layer 153 has formed partly in semiconductor alloy layer 104 and partly on top of the upper surface 104u thereof, which was exposed before depositing the refractory metal layer 108.
As shown in FIG. 1d, after formation of metal silicide layers, preferably nickel silicide layers 162b and 153, a stressed material layer 121 is deposited onto the exposed face of the semiconductor structure 100 by using a well-known deposition technique such as, for example, plasma-enhanced chemical vapor deposition (PECVD). For example, the deposition of the stressed material layer 121 may be performed under a pressure that is in the range of about 300-1200 mTorr, at a temperature between about 400-500° C.
The stressed material layer 121 comprises a dielectric material, typically silicon nitride (SiN), having an etch selectivity to a dielectric material layer 120 formed above the semiconductor structure 100 during a later manufacturing stage (see, e.g., FIG. 1 e). Thus, the stressed material layer 121 also acts as an etch stop layer.
After deposition of the stressed material layer 121, a UV curing process 182 is applied to the semiconductor structure 100 in order to increase the tensile stress of the silicon nitride stressed material layer 121, thus further enhancing the overall speed and performance of the transistor element 150. UV cure 182 is typically performed at a temperature in the range of about 400-500° C.
It has been observed that, mainly as a result of the deposition of the stressed material layer 121 and of UV cure 182, nickel silicide layer 153 forming an interface with SiGe layer 104 in correspondence to the source or drain regions 151 tends to agglomerate into isolated clusters, thus forming holes or voids 153a between neighboring clusters. Thus, the SiGe layer 104 in the source or drain regions 151 forms an interface with the SiN stressed material layer 121 through holes 153a in the nickel silicide layer 153.
Thus, metal silicide layer 153 tends to agglomerate, forming isolated clusters during the fabrication steps performed at a temperature between about 400-500° C. after the formation of metal silicide layer 153.
The presence of a “spotty,” i.e., a clustered, non-continuous metal silicide layer 153 on top of the source and drain regions 151 is highly undesirable during fabrication of the semiconductor structure 100. Since the metal silicide 153 is specifically provided so as to reduce the contact resistance of the transistor 150, the presence of a spotty silicide layer may generally reduce the overall conductivity. Furthermore, a possible negative consequence of the presence of holes 153a in the metal silicide layer 153 is illustrated in FIG. 1e, which schematically illustrates a fabrication process step subsequent to that shown in FIG. 1 d. 
An interlayer dielectric material layer 120 is deposited onto the stressed material layer 121. The dielectric layer 120, which may comprise any suitable dielectric material such as, for example, silicon dioxide (SiO2), is generally deposited as a continuous layer. Thereafter, an etching process 184, such as reactive ion etching (RIE), is performed on the semiconductor structure 100. Etching 184 may be performed after placing an appropriately patterned etching mask 122 on the surface of the structure 100. Etching 184 is performed in order to form via openings 124 and 126 exposing portions of the metal silicide layer 153 contacting the source and drain regions 151 and portions of the metal silicide layer 162b contacting gate electrode material 162, respectively. In particular, etching 184 may be performed in two subsequent steps. In the first step, portions of the dielectric layer 120 are removed by using a selective etching not affecting the stressed material layer 121. In the second step of etch process 184, the portions of the stressed material layer 121 at the bottom of openings 124 and 126 are removed so as to expose underlying portions of metal silicide layers 153 and 162b, respectively.
Due to the presence of the holes 153a in the metal silicide layer 153, during the second step of etching 184, via openings 124 may only partially align with the nickel silicide 153 in and on top of source and drain regions 151, thereby potentially leading to product defects. In particular, the second step of etch 184 might etch deeply into the active region 102a through holes 153a, thereby forming the channels 124pt in the source and/or drain region 151 of the transistor 150.
In a subsequent fabrication step, via openings 124 and 126 are filled with a high electrical conductivity metal such as tungsten. If channels 124pt have been formed during etch 184, they are also filled with tungsten, thus forming a so-called contact “punch through,” i.e., a metallic contact extending within the inside of the source or drain regions 151. Contact “punch throughs” significantly alter the characteristics of the transistor 150, since they may even result in a complete shorting of PN junctions and shortings of adjacent contact elements via the well region of different transistors.
Thus, it is desirable that the metal silicide layer 153 contacting the source and drain regions 151 is continuous and free of holes or cut-out portions.
It has been recognized that the presence of the holes 153a is strongly correlated with the high germanium concentration within the material 153. This hypothesis follows from the observation that metal silicide 153 formed in and on top of source and drain regions 151 and, thus, forming an interface with SiGe layer 104, tends to agglomerate into clusters upon any heating treatment performed at a temperature above about 400° C. after formation of metal silicide 153. By contrast, nickel silicide agglomeration does not occur under deposition of the stressed material layer 121 or exposure to the UV cure 182 in the nickel silicide layer 162b in the upper portion of the gate electrode 160, which is comprised substantially of polysilicon material 162. Accordingly, it is believed that nickel silicide agglomeration may possibly be caused by the presence of germanium, which may tend to “destabilize” the microstructure under exposure to UV light or heating at high temperatures, thereby allowing some degree of nickel silicide and/or silicon/germanium material diffusion to occur.
Avoiding any process with elevated temperatures after incorporating the metal silicide 153 may result in inferior device characteristics and may also significantly restrict the overall flexibility in designing the manufacturing flow for fabricating complex semiconductor devices. Similarly, reducing the germanium concentration is also less than desirable, even if a corresponding reduction in germanium concentration would be restricted to an upper portion of the material 153 since, in particular in highly scaled devices, nevertheless, a pronounced reduction of the overall strain in the channel region 155 may be observed, thereby also reducing overall performance of the transistor 150.
Solutions to these problems have been proposed in the case of P-channel FETs including embedded SiGe, i.e., a semiconductor alloy portion embedded in the active regions at the ends of the channel region, as defined above. Solutions include use of a “cap” layer with a smaller germanium concentration. Other solutions propose to implant impurity ions, such as carbon and nitrogen ions, within a surface portion of the embedded SiGe wherein the nickel silicide layer is later to be formed. This latter approach has been proposed, for example, in U.S. patent applications published as US 2012/0241816 A1 and US 2012/0261725 A1.
However, no approach has been proposed so far for P-channel FETs including a channel semiconductor alloy layer on top of a crystalline silicon active region but no embedded semiconductor alloy. Such P-channel FETs may be, for example, fabricated according to the gate-first HKMG approach.
Thus, an object of the present invention is to provide an improved fabrication method for P-channel FETs having a channel SiGe layer but no embedded SiGe, which is able to alleviate or minimize the drawbacks and problems set forth above. In particular, the present invention proposes a method of fabricating a P-channel FET having a channel SiGe layer and no embedded SiGe, which prevents the metal silicide layer contacting the source and drain regions from agglomerating during the fabrication process flow.